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This paper presents a new class of Computational RAM (C-RAM) architectures for real-time MPEG-4 applications. The proposed C-RAM architecture consists of an embedded SRAM and number of processing elements working in parallel to process the data stored in the memory. The processing elements are working as a single instruction multiple data (SIMD) architecture. Each processing element is used to process one memory column. The proposed class of C-RAM architectures has been used for MPEG-4 block-based motion estimation, which is the most computational intensive task in the encoder. The proposed architecture has been designed, prototyped, and simulated for 0.18 μm CMOS TSMC technology. The simulation results show a promising performance of the proposed class of C-RAM architectures in video coding applications; it can process up to 126 frames per second with clock frequency 100 MHz.
Date of Conference: 30 June-2 July 2003