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The efficient bus arbitration scheme in SoC environment

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4 Author(s)
Chang Hee Pyoun ; Dept. of Electron. Eng., Hanyang Univ., Seoul, South Korea ; Chi Ho Lin ; Hi Seok Kim ; Jong Wha Chong

This paper presents the dynamic bus arbiter architecture for a system on chip design. The conventional bus-distribution algorithms, such as the static fixed priority and the round robin, show several defects that are bus starvation, and low system performance because of bus distribution latency in a bus cycle time. The proposed dynamic bus architecture is based on a probability bus distribution algorithm and uses an adaptive ticket value method to solve the impartiality and starvation problems. The simulation results show that the proposed algorithm reduces the buffer size of a master by 11% and decreases the bus latency of a master by 50%.

Published in:

System-on-Chip for Real-Time Applications, 2003. Proceedings. The 3rd IEEE International Workshop on

Date of Conference:

30 June-2 July 2003