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In this paper, we are proposing an efficient design space exploration methodology based on a component point of view to system-on-a-chip (SOC) designs. The core is described behaviorally in VHDL and then, to reach the final implementation, the design process goes through architecture selection, scheduling, pipelining and module selection processes. As it enters any phase, it is explored by a local exploration scheme incorporated within that phase. Therefore, at minimum, a 3D design space exploration methodology is always granted. However, the proposed methodology structure reflects the current state-of-the-art behavioral synthesis process.