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Power consumption and portability issues are increasingly significant in system-on-a-chip applications. As a result, it is important that power and performance tradeoffs are made more visible to chip architects and circuit designers. Next generation tools are being developed to achieve high accuracy by estimating power consumption earlier in the design process. These tools also allow the designer to explore different configurations in a given design space. As the design space continues to expand, more efficient search methods are needed. This paper presents a framework for an evolutionary approach to configuring an ideal embedded processor based on power consumption.