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Dynamic hardware-software partitioning on reconfigurable system-on-chip

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2 Author(s)
Waldeck, P. ; Sch. of ITEE, Queensland Univ., Brisbane, Qld., Australia ; Bergmann, N.

This paper introduces a computer architecture suitable for embedded real-time applications where low power consumption is a requirement. This is achieved through the use of a hybrid hardware-software system. A system architecture is proposed which allows for modules of a system to be implemented in either hardware or software. Implementation choices may be made dynamically based on the loading of the host microprocessor, in a multi-tasking environment. An approach to inter-module communications is described along with how this is affected by dynamic configuration. Acoustic echo cancellation through the use of the maximal length correlation technique is used as an application example. Implementation as a hybrid hardware-software system is examined. An example partitioning arrangement shows total bus bandwidth utilization to be approximately 1%.

Published in:

System-on-Chip for Real-Time Applications, 2003. Proceedings. The 3rd IEEE International Workshop on

Date of Conference:

30 June-2 July 2003

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