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Energy optimization in a HW/SW tool: design of low power architecture system

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3 Author(s)
Guitton-Ouhamou, P. ; Lab. d'Informatique, Signaux et Systemes de Sophia-Antipolis, France ; Belleudy, C. ; Auguin, M.

Minimizing power consumption in system on chip is a crucial task. So the parameter of consumption has to be introduced in HW/SW tool. This paper describes how our HW/SW codesign tool, CODEF, is extended to have power consumption and optimization ability. Some strategies of consumption optimizations are presented. First, we present how to build the library composed of consumption models of hardware and software modules (that take into account frequency and supply voltage). Then, we describe the algorithm that computes the peak power and the energy. To reduce the energy, we describe a strategy during allocation step to minimize energy. In this way, the partitioning algorithm has been modified and we present some results of architectures optimization with some important gains of 50%.

Published in:

System-on-Chip for Real-Time Applications, 2003. Proceedings. The 3rd IEEE International Workshop on

Date of Conference:

30 June-2 July 2003