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A 1 V 2.4 GHz-band fully monolithic PLL synthesizer was fabricated using 0.2 /spl mu/m CMOS/SOI process technology. It includes a voltage controlled oscillator (VCO) and a 3 GHz fully differential dual-modulus prescaler on a chip. A low-off-leakage-current charge pump is used for open-loop FSK modulation. When the PLL is in open loop mode, the frequency drift of the output is lower than 2.5 Hz//spl mu/sec. The output phase noise is -104 dBc/Hz at 1 MHz offset frequency. The power consumption of the PLL-IC core is 17 mW at 1 V supply voltage.