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Implementation of phase-mode arithmetic elements for parallel signal processing

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5 Author(s)
Onomi, T. ; Lab. for Electron. Intelligent Syst., Tohoku Univ., Sendai, Japan ; Horima, Y. ; Kobori, M. ; Shimizu, I.
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We report the preliminary designs and the experimental results of high-speed digital processing elements based on phase-mode logic circuits. The core cell of these elements is a bit-serial adder cell consisting of the ICF gate which is the basic gate of phase-mode logic. Our main target is the application of the logic circuits to Digital Signal Processing. The basic arithmetic operations of DSP are a multiplication and an addition. Basic concept of the phase-mode pipelined parallel multiplier has been proposed previously. We design a 2 × 2 AND array block and a 2-bit ripple-carry adder for the primitive parallel pipelined multiplier and also a 2-bit subtractor with a pipelined structure. These processing elements have been fabricated using NEC standard 2.5 kA/cm2 Nb/AlOx/Nb process. The low-speed test results of these elements show correct operations. Numerical simulations show that a carry save adder (a 2-bit ripple carry adder) can operate over 10 GHz. We also discuss the prospects of large-scale SFQ DSP based on Nb junction technology.

Published in:

Applied Superconductivity, IEEE Transactions on  (Volume:13 ,  Issue: 2 )

Date of Publication:

June 2003

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