By Topic

Design and demonstration of SFQ pipelined multiplier

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
A. Akahori ; Dept. of Quantum Eng., Nagoya Univ., Japan ; M. Tanaka ; A. Sekiya ; A. Fujimaki
more authors

We have designed an SFQ pipeline multiplier using a cell-based design method. The cell-based design method enables us to expand the circuit-scale easily and is essential for the design of large-scale circuits. In the construction of the multiplier, a serial-parallel type was adopted. This type performs the partial products and the summation of the products in a bit-serial form. The multiplier designed here is a 3-bit serial-parallel structure with a seven-stage pipeline and is composed of destructive read-out (DRO) gates, nondestructive read-out (NDRO) gates and carry save serial adders (CSSA's). This circuit was fabricated by the NEC standard process. The number of Josephson Junctions is 1150. We have successfully tested the full operation with a bias margin of ±5.5%.

Published in:

IEEE Transactions on Applied Superconductivity  (Volume:13 ,  Issue: 2 )