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Design and component test of SFQ shift register memories

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4 Author(s)
Fujiwara, K. ; Dept. of Electr., Yokohama Nat. Univ., Japan ; Hoshina, H. ; Yamashiro, Y. ; Yoshikawa, N.

The lack of a high-density and high-speed memory is a serious impediment for realization of large-scale RSFQ digital systems. A shift resister memory, which has high throughput and simple circuit structure, is one candidate to overcome this drawback. We show a design framework of the shift register memory, which is usable for the high-speed register files and the main memories of the RSFQ microprocessor. The proposed system consists of an array of shift registers and a packet decoder that switches a high-speed serial data stream into the specified shift register. The target clock frequency is 16 GHz assuming 2.5 kA/cm2 Nb standard process. We have estimated the propagation delay and the circuit area of the data-driven self-timed (DDST) packet decoder. Based on this estimation, we have also evaluated the access time and the area of the memory system. Several key components, including the one-to-two packet switch and the one-to-four DDST packet decoder, were implemented and their correct operations were confirmed.

Published in:

Applied Superconductivity, IEEE Transactions on  (Volume:13 ,  Issue: 2 )