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Several programs exist that calculate inductance in line structures. Some can even handle corners and holes in the ground plane. However, real structures in superconducting electronics are often more complex, and more elaborate techniques are needed to provide a reliable estimate of inductance, especially over very short intra-gate distances. A technique implemented with a modified version of FastHenry is discussed, whereby any inter-junction inductance in RSFQ circuits, in the vicinity of complex three-dimensional structures, junction cover pads and damping resistors, can be estimated. Placement of the reflection plane for the method of images is also discussed, together with the effect of segmentation size, and various results presented.