By Topic

RSFQ random logic gate density scaling for the next-generation Josephson junction technology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
P. Bunyk ; Space & Electron., TRW Inc., Redondo Beach, CA, USA

Post-layout automatic analysis of Flux-1 microprocessor, a representative random logic RSFQ chip of more than 5000 gate complexity, allowed us to extract important layout parameters such as gate density, Josephson junction density and gate/wiring/unused area ratios. A scaling model is presented to predict the area required to layout a given number of random logic gates. When applied to Flux-1 chip itself, which occupies 88.6 mm2 in the current TRWs 4 kA/cm2 J110D technology, this model predicts that it can be shrunk by almost a factor of two in area to 49 mm2 if moved to a next-generation J110E technology with 8 kA/cm2 junctions. This information enables us to confidently floorplan random logic chips to be implemented in future advanced JJ technologies. It can also provide directions for JJ technology improvements leading to the maximum positive impact on RSFQ chip density.

Published in:

IEEE Transactions on Applied Superconductivity  (Volume:13 ,  Issue: 2 )