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Multiple-chip module design optimizations using a novel layout parameterization technique

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5 Author(s)
Chun-Wen Huang ; Anadigics Inc., Warren, NJ, USA ; Dow, G.S. ; Jianwen Bao ; Kuran, S.
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A novel layout parameterization technique for multi-chip module design optimizations is presented. This technique is based on a quasi-static method of moments and multi-dimensional interpolation, which can reduce a 12-minute electromagnetic layout simulation to 5.3 seconds. Excellent CDMA power amplifier (PA) module performance is achieved based on this technique.

Published in:

Microwave Symposium Digest, 2003 IEEE MTT-S International  (Volume:1 )

Date of Conference:

8-13 June 2003