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This paper discusses the design of Direct Digital Frequency Synthesizers (DDFS) based on the linear interpolation of the sine function. The problem of approximating the sine function within a desired error bound is specifically considered. The use of linear segments is favorable for hardware implementation because of the low processing complexity requirements. A relation between the minimum number of linear segments, the resolution with which segment slopes are expressed, and the achievable precision is derived. Tradeoffs between memory storage requirements and computational complexity are identified, and architectural and implementation issues are discussed. Example designs achieving; 8, 10 and 12 bits of amplitude resolution with 59, 77 and 86 dBc of Spurious Free Dynamic Range (SFDR) are presented.