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Performance advantage of Schottky source/drain in ultrathin-body silicon-on-insulator and dual-gate CMOS

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3 Author(s)
Connelly, D. ; Acorn Technol., Palo Alto, CA, USA ; Faulkner, Carl ; Grupp, D.E.

Here, for the first time, advanced simulation models are used to investigate the performance advantage of Schottky source/drain ultrathin-silicon technologies at a 25-nm gate length target. Schottky and doped source/drain MOSFETs were optimized and compared using a novel benchmark. Mixed-mode simulations of optimized devices in a two-stage NAND chain show an approximate 45% speed advantage of Schottky source/drain for one set of parameter choices. Contact requirements for Schottky source/drain, and for doped source/drain relative to ITRS targets through 2016, are discussed.

Published in:

Electron Devices, IEEE Transactions on  (Volume:50 ,  Issue: 5 )

Date of Publication:

May 2003

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