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A true single-phase energy-recovery multiplier

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3 Author(s)
Suhwan Kim ; Dept. of Electr. Eng. & Comput. Sci., Univ. of Michigan, Ann Arbor, MI, USA ; Ziesler, C.H. ; Papaefthymiou, M.C.

In this paper, we present the design and experimental evaluation of an 8-bit energy-recovery multiplier with built-in self-test logic and an internal single-phase sinusoidal power-clock generator. Both the multiplier and the built-in self-test have been designed in SCAL-D, a true single-phase adiabatic logic family. Fabricated in a 0.5-/spl mu/m standard n-well CMOS process, the chip has an active area of 0.47 mm/sup 2/. Correct chip operation has been verified for clock rates up to 140 MHz. Moreover, chip dissipation measurements correlate well with HSPICE simulation results. For a selection of biasing conditions that yield correct operation at 140 MHz, total measured average dissipation for the multiplier and the power-clock generator is 250 pJ per operation.

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:11 ,  Issue: 2 )