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Driver modeling and alignment for worst-case delay noise

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3 Author(s)
Blaauw, D. ; Univ. of Michigan, Ann Arbor, MI, USA ; Sirichotiyakul, S. ; Chanhee Oh

In this paper, we present a new approach to model the impact of cross-coupling noise on interconnect delay. We introduce a new linear driver model that accurately models the noise pulse induced on a switching signal net due to cross-coupling capacitance. The proposed model effectively captures the nonlinear behavior of the victim-driver gate during its transition and has an average error below 8% whereas the traditional approach using a Thevenin model incurs an average error of 48%. The proposed linear driver model enables the use of linear superposition which allows the analysis of large interconnects and an efficient determination of the worst-case transition times of the aggressor nets. We proposed a new approach to determine the worst-case alignment of the aggressor net transitions with respect to the victim net transition, emphasizing the need to maximize not merely the delay of the interconnect alone but the combined delay of the interconnect and receiver gate. We show that in the presence of multiple aggressor nets, the worst case delay may occur when their noise peaks are not aligned, although the error incurred from aligning all peaks is small in practice. We then show that the worst-case alignment time of the combined noise pulse from all aggressors with respect to the victim transition is a nonlinear function of the receiver gate output loading, the victim transition time, and the noise pulsewidth and height. To efficiently compute the worst-case alignment time, we propose a new representation of the alignment such that it closely fits a linear function of the input variables. The worst-case alignment time is then computed for a gate using a precharacterization approach, requiring only eight sample points while maintaining a small error. The proposed methods were implemented in an industrial noise analysis tool called ClariNet. Results on industrial designs, including a large PPCmicroprocessor design, are presented to demonstrate the effectiveness of our approach.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:11 ,  Issue: 2 )

Date of Publication:

April 2003

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