Referenced Items are not available for this document.
We present the formal verification of an Intel Xscale processor model. The Xscale is a superpipelined RISC processor with 7-stage integer, 8-stage memory, and variable-latency multiply-and-accumulate execution pipelines. The processor uses scoreboarding to track data dependencies, and implements both precise and imprecise exceptions. Such set of features had not been modeled and formally verified previously. The formal verification was done with an automatic tool flow that consists of the term-level symbolic simulator TLSim, the decision procedure EVC, and an efficient SAT-checker.
Published in:
Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings. First ACM and IEEE International Conference on
Date of Conference: 24-26 June 2003
- Page(s):
- 65 - 74
- Print ISBN:
- 0-7695-1923-7
- INSPEC Accession Number:
- 7810214
- Conference Location :
- Mont Saint Michel, France
- Digital Object Identifier :
- 10.1109/MEMCOD.2003.1210090
- Product Type:
- Conference Publications
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