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A two-stage distributed shared memory architecture and its scheduling algorithms

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4 Author(s)
Yi Peng ; Nat. Digital Switching Syst. Eng. & Technol. R&D Center, Zhengzhou, China ; Yuguo Dong ; Jinwu Wei ; Yunfei Guo

The performance of a high-speed router is limited by the random access rate of memories and the switching rate of the inner switch architecture. This paper proposes a two-stage distributed shared memory architecture (TSDSM) and its scheduling algorithms which can emulate the FCFS and the PIFO output-queued (OQ) scheduling algorithms. The lower bound of the memories of the TSDSM is analyzed. We also prove that our algorithms can emulate the QQ scheduling algorithms. The most advantage of the TSDSM over other switching architectures is that the access rate of the memories is commercially available and the switch can work without speedup.

Published in:

Communication Technology Proceedings, 2003. ICCT 2003. International Conference on  (Volume:1 )

Date of Conference:

9-11 April 2003

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