Referenced Items are not available for this document.
Two eight-state 7-bit soft-output Viterbi decoders matched to an EPR4 channel and a rate-8/9 convolutional code are implemented in a 0.18-μm CMOS technology. The throughput of the decoders is increased through architectural transformation of the add-compare-select recursion, with a small area overhead. The survivor-path decoding logic of a conventional Viterbi decoder register exchange is adapted to detect the two most likely paths. The 4-mm2 chip has been verified to decode at 500 Mb/s with 1.8-V supply. These decoders can be used as constituent decoders for Turbo codes in high-performance applications requiring information rates that are very close to the Shannon limit.
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:38
,
Issue:
7
)
Date of Publication: July 2003
- Page(s):
- 1234 - 1241
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 7688509
- Digital Object Identifier :
- 10.1109/JSSC.2003.813250
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 09 July 2003
- Issue Date :
- July 2003
- Sponsored by :
- IEEE Solid-State Circuits Society
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