Referenced Items are not available for this document.
A high-resolution multibit sigma-delta analog-to-digital converter (ADC) implemented in a 0.18-μm CMOS technology is introduced. The circuit is targeted for an asymmetrical digital subscriber line (ADSL) central-office (CO) application . An area- and power-efficient realization of a second-order single-loop 3-bit modulator with an oversampling ratio of 96 is presented. The ΣΔ modulator features an 85-dB dynamic range over a 300-kHz signal bandwidth. The measured power consumption of the ADC core is only 15 mW. An innovative biasing circuitry is introduced for the switched-capacitor integrators.
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:38
,
Issue:
7
)
Date of Publication: July 2003
- Page(s):
- 1105 - 1114
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 7688496
- Digital Object Identifier :
- 10.1109/JSSC.2003.813216
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 09 July 2003
- Issue Date :
- July 2003
- Sponsored by :
- IEEE Solid-State Circuits Society
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