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Fault equivalence identification in combinational circuits using implication and evaluation techniques

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4 Author(s)
M. E. Amyeen ; Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; W. K. Fuchs ; I. Pomeranz ; V. Boppana

Efficient identification of fault equivalence relations is essential for effective diagnostic test pattern generation. In this paper, we present efficient techniques for identifying functionally equivalent faults in combinational circuits. The techniques are based on implication of faulty values, and evaluation of faulty functions in cones of dominator gates of fault pairs. This is enhanced by utilizing circuit redundancy information. Both static and dynamic methods are developed to exploit relations among inputs of dominator cones and further speed up the identification of equivalent fault pairs. Experimental results for all ISCAS'85 circuits, full scan versions of ISCAS'89 circuits, and ITC'99 circuits show that most of the equivalent fault pairs are identified. Significant reductions are obtained in the runtime needed to prove equivalence and the runtime for diagnostic test pattern generation compared to previously proposed approaches.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:22 ,  Issue: 7 )