By Topic

Modeling double-layer capacitor behavior using ladder circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
R. M. Nelms ; Dept. of Electr. & Comput. Eng., Auburn Univ., AL, USA ; D. R. Cahela ; B. J. Tatarchuk

The double-layer capacitor (DLC) is a very complex device that is best represented by a distributed parameter system. Many different lumped-parameter equivalent circuits have been proposed for the DLC. An examination into utilizing a ladder circuit to model a DLC is presented. Parameters for different ladder circuits are determined from AC impedance data. Variations in circuit parameters with DC bias and manufacturing have been investigated. The performance of the ladder circuit has been evaluated in slow discharge and pulse load applications.

Published in:

IEEE Transactions on Aerospace and Electronic Systems  (Volume:39 ,  Issue: 2 )