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A pipelined memory architecture for high throughput network processors

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3 Author(s)
T. Sherwood ; Dept. of Comput. Sci. & Eng., California Univ., San Diego, CA, USA ; G. Varghese ; B. Calder

Designing ASICs for each new generation of backbone routers is a time intensive and fiscally draining process. We focus on the design of a programmable architecture for backbone routers, based on the manipulation of wide irregular memory words, that can provide a feasible design alternative to custom ASICs. We propose a pipelined memory design that emphasizes worst-case throughput over latency, and coexplore architectural tradeoffs with the design of several important network algorithms. Through this coexploration, we show that a programmable architecture can efficiently exploit behavior inherent to most common network algorithms to keep up with next generation network speeds.

Published in:

Computer Architecture, 2003. Proceedings. 30th Annual International Symposium on

Date of Conference:

9-11 June 2003