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In this paper, we propose the combination of triple algorithm redundancy and vote-writeback mechanism for realizing concurrently error correctable Register Transfer (RT) level datapath of a specified computation algorithm. The vote-writeback mechanism will be introduced to reduce wire complexity around voters compared with other conventional voting scheme. Even though the vote-writeback mechanism can not correct erroneous data on a faulty register, the overall fault tolerance of the datapath with respect to any single fault in the datapath part can be guaranteed by this vote-writeback mechanism and appropriate insertion of voters.
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on (Volume:5 )
Date of Conference: 25-28 May 2003