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BIST for clock jitter measurements

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3 Author(s)
Kuo-Hsing Cheng ; Dept. of Electr. Eng., Tamkang Univ., Tamsui, Taiwan ; Shu-Yu Jiang ; Zong-Shen Chen

In high-speed circuit testing, traditional methods are inadequate for measuring clock jitter. In order to achieve more consistent clock jitter measurement, a Time to Digital Converter (TDC) technique is used to output all-digital data. A Built-In-Self-Test (BIST) method is used to realize the proposed method. However, even for some proposed BIST methods, the requirements of test time and circuit area still limit the circuit application. In order to release this requirement, a new BIST method is presented. A continuous clock jitter measurement method is adopted to make a real-time measurement. With the proposed pre-delayed sample clock, no more extra delay cells are needed. The circuit area and test time can be significantly reduced. Furthermore, with an improved circuit structure, the circuit stability can be increased and no external jitter-free clock is needed to sample the clock jitter.

Published in:

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on  (Volume:5 )

Date of Conference:

25-28 May 2003

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