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A tester-on-chip implementation in 0.18μ CMOS utilizing a MEMS interface

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3 Author(s)
R. Rashidzadeh ; Windsor Univ., Ont., Canada ; M. Ahmadi ; W. C. Miller

This paper proposes a new technique for testing a core based system-on-chip (SoC). The novel feature of the approach is the use of a SoC implementation of a tester-on-chip (ToC) together with a microelectromechanical systems (MEMS) test socket instead of traditional test head. This method greatly reduces transmission line effects and supports high speed bi-directional testing. A tester-on-chip is installed in a fixed MEMS socket and connects to the die-under-test (DUT) via a removable MEMS interface. At-speed tests are carried out inside the ToC, while test results and control signals are transferred between the automatic test equipment (ATE) and ToC at low speed. Our approach eliminates the necessity of using matched impedance interfaces, costly test heads and a high-speed ATE for SoC testing and dramatically decreases the cost of SoC testing. The results in this paper are based on design and simulation studies.

Published in:

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on  (Volume:5 )

Date of Conference:

25-28 May 2003