Performance modeling of resonant tunneling based RAMs

Tunneling based random-access memories (TRAM's) have recently garnered a great amount of interests among the memory designers due to their intrinsic merits such as reduced power consumption by elimination of refreshing operation, faster read and write cycles, and improved reliability in comparison to conventional silicon DRAM's. In order to understand the precise principle of operation of TRAM's, an in-depth circuit analysis has been attempted in this paper and analytical models for memory cycle time, soft error rate, and power consumption have been derived. The analytical results are then validated by simulation experiments performed with HSPICE. These results are then compared with conventional DRAM's to establish the claim of superiority of TRAM performance to DRAM performance.