Combinational circuit fault diagnosis using logic emulation

We propose an emulation-based diagnosis technique for combinational circuits in this paper. To verify our approach, a hardware emulator is implemented by using Altera MAX+Plus II CPLD Development System. Our approach reduces the CPU time required by a software-based diagnosis technique significantly, and greatly eliminates the hardware requirements with circuit partitioning techniques and novel fault injection elements (FIEs). Moreover, our diagnosis algorithm also decreases the times of simulation when performing diagnosis. Experimental results for ISCAS-85 benchmark circuits show that our emulation system is 45 times faster than Kokan's (1999) on the average.