By Topic

Experimental evaluation and validation of a BIST algorithm for characterization of A/D converter performance

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
K. L. Parthasarathy ; Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA ; Le Jin ; T. Kuyel ; D. Price
more authors

A new histogram based algorithm for characterization of analog-to-digital converters has been introduced. The proposed method is based on using a highly nonlinear but stationary signal, which can be easily and practically generated on chip. This not only relaxes the requirement on the signal generator, but also enables the use of fast sources, thereby reducing test time and test costs. Experimental test results on commercially available 10 bit pipelined ADCs indicate that the algorithm can estimate the linearity specifications of the device to within 0.5 LSB by using an input signal of just 2 bit linearity.

Published in:

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on  (Volume:5 )

Date of Conference:

25-28 May 2003