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Statistical modeling of gate-delay variation with consideration of intra-gate variability

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3 Author(s)
Okada, K. ; Dept. of Commun. & Comput. Eng., Kyoto Univ., Japan ; Yamaoka, K. ; Onodera, Hidetoshi

This paper proposes a model to calculate statistical gate-delay variation caused by intra-chip and inter-chip variabilities. The variation of each gate delay directly influences the variation of circuit delay, so it is important to characterize each gate-delay variation accurately. Our model characterizes the gate delay by transistor characteristics. Every transistor in a gate affects the transient characteristics of the gate, so it is indispensable to consider the intra-gate variability for the modeling of gate-delay variation. This effect is not captured in a statistical delay analysis reported so far. Our model characterizes a statistical gate-delay variation using a response surface method (RSM) and represents the intra-gate variability with a few parameters. We evaluate the accuracy of our model, and we show some simulated results of a circuit delay variation.

Published in:

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on  (Volume:5 )

Date of Conference:

25-28 May 2003