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High performance asynchronous bus for SoC

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3 Author(s)
Eun-Gu Jung ; Dept. of Inf. & Commun., Kwangju Inst. of Sci. & Technol., Gwangju, South Korea ; Byung-Soo Choi ; Dong-Ik Lee

It is difficult to use synchronous buses in a system-on-a-chip design due to the increase of wire delay caused by the crosstalk effect and the difficulty of the synchronization caused by the clock-skew problem. The use of an asynchronous bus is an alternative solution for the SoC design method. In this paper, we propose a new high performance asynchronous bus using a return-to-zero data encoding method to get a low latency and a high throughput as well. Simulation results reveal that, by the proposed scheme, the read throughput increases by 17.6%, and the read latency decreases by 12.5% simultaneously.

Published in:

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on  (Volume:5 )

Date of Conference:

25-28 May 2003