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The design of robust and area efficient power distribution networks for high speed, high complexity integrated circuits has become a challenging task. The integrity of the high frequency signals depends upon the impedance characteristics of the on-chip power distribution networks. The electrical characteristics of these multi-layer power distribution grids and the relevant design implications are the subject of this paper. Each grid layer within a multilayer power distribution grid typically has significantly different electrical properties. Unlike single layer grids, the electrical characteristics of a multi-layer grid can vary significantly with frequency. As the frequency increases, a large share of the current flow is transfered from the low resistance upper layers to the low inductance lower layers. The inductance of a multi-layer grid therefore decreases with frequency, while the resistance increases with frequency. Therefore, as compared to power distribution grids built exclusively in the upper, low resistance metal layers, a multi-layer power distribution grid extending to the lower interconnect layers exhibits superior high frequency impedance characteristics. An analytic model is also presented to determine the impedance characteristics of a multi-layer grid from the inductive and resistive properties of the comprising individual grid layers.