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Many new dynamic logic family techniques require a chain of delayed clocks separated by a time that is usually less than a buffer delay. This paper presents a technique to generate these clocks and distribute them to the logic gates. The system has tuning abilities so that even with process-voltage-temperature (PVT) variation in the distribution paths, it can correct itself. Extraction results for a 0.18um process showed +/- 3ps deviation from a nominal 50ps clock separation for a chain of 10 clocks at 1GHz.