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On chip Gaussian processing for high resolution CMOS image sensors

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2 Author(s)
Vinayagamoorthy, S. ; Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada ; Hornsey, R.

Spatial image processing chips, known as silicon retinas, are based on the architecture of vertebrate retina and call be mathematically represented as the Laplacian of Gaussian (LOG) and Difference of Gaussian (DOG). In this paper, attention has been paid on implementing a retina function through the LOG model. Previous implementations have used a hexagonal resistive mesh within the pixel array, which can lead to low resolutions and difficulty of readout. Here, a rectangular resistive array is designed separate from the pixel array. Placing the resistive mesh at the bottom of the array allows for image sensors with high resolution. New circuits designed to accomplish this separation are reported here. Coupled with an array of photo diode pixels, it may be used for image smoothing and edge detection. The image kernel is 5×5 pixels and is implemented in analog CMOS circuits using a standard 0.35-micron process. The IC was fabricated and the hardware implementation was validated through physical testing.

Published in:

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on  (Volume:4 )

Date of Conference:

25-28 May 2003