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Low-power CMOS circuit techniques for motion estimators

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2 Author(s)
Enomoto, T. ; Graduate Sch. of Sci. & Eng. Inf. & Syst. Eng. Course, Chuo Univ., Tokyo, Japan ; Ei, T.

To drastically reduce the active power (PAT) and the stand-by power (PST) of the CMOS motion estimator (ME), several power reduction techniques were developed. They were circuit architectures that were able to reduce supply voltages (VD) and numbers of logic gates, a fast motion estimation algorithm, and a leakage current reduction circuit. A 0.13-μm CMOS accumulation-type ME (AME) LSI has been developed by using those techniques. At clock frequency of 220 MHz and VD of 0.73 V, PAT was reduced to 51.2 μW, which was 16.3% that of a conventional AME. PST was 9.92 nW, which was 9.58% that of the conventional AME.

Published in:

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on  (Volume:5 )

Date of Conference:

25-28 May 2003