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A power efficient register file architecture using master latch sharing

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6 Author(s)
Wroblewski, M. ; Munich Univ. of Technol., Germany ; Mueller, M. ; Wortmann, A. ; Simon, S.
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This paper introduces a method of reducing area and power consumption of a synthesizable register file by using a single master latch shared by a number of slaves. It investigates potential timing problems and discusses possible solutions. Presented simulation results show that, depending on the size of the register file, reduction of power consumption of more than 50% is achievable.

Published in:

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on  (Volume:5 )

Date of Conference:

25-28 May 2003

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