By Topic

DSP engine for ultra-low-power audio applications [codec application]

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
R. C. S. Morling ; Appl. DSP & VLSI Res. Group, Westminster Univ., London, UK ; I. Kale ; S. J. Morris ; F. Custode

An ultra-low-power DSP decimation/interpolation structure is described demonstrating how algorithmic and architectural schemes were employed for ultimate power efficiency in a DSP based chip set for audio applications. This circuit was designed and synthesised for a low VT 0.35 μm CMOS process allowing Nyquist rate signals to be decimated from a high OSR Σ-Δ front-end and interpolation post voice processing at the back end. The DSP has been fabricated and operates down to 0.9 V. At 1.25 V, its current consumption is only 90 μA.

Published in:

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on  (Volume:5 )

Date of Conference:

25-28 May 2003