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A triple port RAM based low power commutator architecture for a pipelined FFT processor

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2 Author(s)
Hasan, M. ; Dept. of Electron. & Electr. Eng., Edinburgh Univ., UK ; Arslan, T.

This paper proposes a low power commutator architecture based on triple port RAMs rather than dual port RAMs or conventional FIFO for the radix-4 pipelined FFT processor implementation. The triple port RAM based commutator consumes less power than the other two for the first and second stages of a 64-point radix-4 pipelined FFT processor. This commutator is attractive for shorter FFTs but can also be used in the last stages of longer FFTs. Up to 29% and 9% power savings is achieved for the 8-12 bit data range in the second and first stages of a 64-point FFT processor respectively.

Published in:

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on  (Volume:5 )

Date of Conference:

25-28 May 2003

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