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Design of a 32-bit squarer - exploiting addition redundancy

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2 Author(s)
Al-Khalili, A.J. ; Concordia Univ., Montreal, Que., Canada ; Aiping Hu

In this paper, a new architecture for signed and unsigned binary number squarer is given. The method is applied to the design of a 32-bit squarer using Wallace-tree and carry select adder. The proposed design is analytically compared with the conventional designs. For quantitative analysis, the squarer and general-purpose multipliers are synthesized in FPGA using Xilinx 4052x1-1 FPGA technology. The experimental results demonstrate the effectiveness of the proposed method in terms of delay, power and area reduction.

Published in:

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on  (Volume:5 )

Date of Conference:

25-28 May 2003