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A novel logic family called no-race charge recycling complementary pass transistor logic (NCRCPL) has been proposed and analyzed. NCRCPL consumes less power with smaller delay compared to the previously reported logic families based on charge recycling. It has an additional benefit of reduced sensitivity to signal skew. Using a new regenerator in NCRCPL leads to complete elimination of a controller in the circuit, hence the number of transistors was greatly reduced. Considerable improvements in the parameters are confirmed by simulating a two input NAND gate and a full adder using similar styles.