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Macromodel for short circuit power dissipation of submicron CMOS inverters and its application to design CMOS buffers

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1 Author(s)
Ulman, S. ; Dept. of Phys., Goa Univ., India

The paper presents a physical and scalable macromodel of submicron CMOS inverters for short circuit power estimation. The macromodel, which is based on the equivalent capacitance concept, can be used to directly compare the short circuit power dissipation and dynamic power dissipation. The validity of the model is estimated by comparing it with the simulated values (SPICE level 3 model). The macromodel is useful in power and delay optimization of a CMOS buffer chain.

Published in:

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on  (Volume:5 )

Date of Conference:

25-28 May 2003