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Conventional ASIC designs are hard to customize. Therefore DSP core-based ASIC design has a potentially large payoff. This approach not only supports improved performance but also shortens the time-to-market. An embedded DSP was proposed, and for better performance and flexibility we design a parameterized and low power DSP core generator. A dual MAC unit, sub-word multiplier, and some function-specific blocks are adapted to accelerate communication system applications. The Gray code addressing mode, pipeline sharing and advanced hardware looping are designed to reduce power consumption at the architecture level. The generator uses a graphical user interface (GUI) and can generate synthesizable Verilog code of the embedded DSP core according to user specifications.