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This paper addresses the design of source-coupled logic (SCL) gates, extending previous results obtained in the simple case of an inverter. The design strategy is applied to MUX, XOR and D-latch SCL gates, and is based on a simple model of their speed and noise margin. Design equations are found to size bias current and transistors' aspect ratio for assigned constraints on speed, power consumption and noise immunity. The expressions found are sufficiently simple for pencil-and-paper calculations and highlight the tradeoffs involved in the design. Simple design criteria are derived in typical design cases where a high speed, a low power consumption or a tradeoff are targeted. Results are validated by extensive simulations on a 0.35 μm CMOS process.