Area efficient, high speed parallel counter circuits using charge recycling threshold logic

The main result is the development of a low depth, highly compact implementation of parallel counters (i.e., population counters), based on threshold logic. Two such counters are designed using the recently proposed Charge Recycling Threshold Logic (CRTL) gate. The novel feature of the designs is the sharing among all threshold gates of a single capacitive network for computing the weighted sum of all input bits. The significance of the result is the reduction by almost 35% in the required number of capacitors for the (7,3) counter and by over 60% for the (15,4) counter. This reduces the total area by approximately 37% for the (7,3) counter and by 60% for the (15,4) counter, with no increase in delay. The proposed (7,3) counter design is also shown to be 45% faster compared to a conventional Boolean full-adder based circuit.