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A systematic methodology for designing area-time efficient parallel-prefix modulo 2n - 1 adders

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4 Author(s)
G. Dimitrakopoulos ; Dept. of Comput. Eng. & Inf., Patras Univ., Greece ; H. T. Vergos ; D. Nikolos ; C. Efstathiou

In this paper a systematic methodology for designing parallel-prefix modulo 2n - 1 adders, for every n, is introduced. The resulting modulo 2n - 1 adders feature minimum logical depth and bounded fan-out loading. Additionally, an optimization technique is proposed, which aims at the reduction of redundant operators that appear on the parallel-prefix carry computation trees. Performance data reveal that the reduced structures achieve area × time complexity reduction of up to 46% when compared to previously reported designs.

Published in:

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on  (Volume:5 )

Date of Conference:

25-28 May 2003