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Modulo (2p ± 1) multipliers using a three-operand modular addition and Booth recoding based on signed-digit number arithmetic

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2 Author(s)
Wei, S. ; Dept. of Comput. Sci., Gunma Univ., Japan ; Shimizu, K.

A new three-operand modulo (2p ± 1) addition is presented, performing a carry-save addition and a two-operand modular addition based on the p-digit radix-two signed-digit (SD) number system. When a modulo (2p ± 1) multiplier is constructed as a ternary tree structure with the three-operand modular adders, the modular multiplication time is proportional to log3p. When a serial modular multiplier is constructed, we give two architectures using the two-operand and three-operand modular adders, respectively. A Booth recoding method is also proposed to reduce the modular partial products. The design and simulation results by VHDL show that high speed modular multipliers can be obtained by the presented algorithms.

Published in:

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on  (Volume:5 )

Date of Conference:

25-28 May 2003