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An efficient transistor optimizer for custom circuits

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3 Author(s)
Xiao Yan Yu ; Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA ; V. G. Oklobdzija ; W. W. Walker

We present an equation-based transistor size optimizer that minimizes delay of custom circuits. Our method uses static timing analysis to find the critical paths and numerical methods to optimize transistor sizes continuously without using simulation. Consequently, it is faster than simulation-based optimizers, and more general than standard cell optimizers. We demonstrate its efficacy and accuracy on a complete dynamic adder presented, where we achieve a 54% speed-up, and final critical path delay that match Spice within 1%.

Published in:

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on  (Volume:5 )

Date of Conference:

25-28 May 2003