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History-based memory mode prediction for improving memory performance

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2 Author(s)
Seong-Il Park ; Dept. of EECS, KAIST, Daejeon, South Korea ; In-Cheol Park

To increase the bandwidth of synchronous memories that are widely adopted for high performance memory systems, a predictive mode control scheme is proposed in this paper. Memory latency can be reduced by effectively managing the states of banks. The local access history of each bank is considered to predict the memory mode. Experimental results show that the proposed scheme, at the cost of negligible area overhead, reduces the memory latency by 19.0% over the conventional scheme that always keeps the memory in idle state.

Published in:

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on  (Volume:5 )

Date of Conference:

25-28 May 2003