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This paper presents a novel (low arithmetic unit count) hardware architecture for performing lifting-based JPEG2000's 5/3 Discrete Wavelet Transform (DWT). The architecture is built around parallel Shift-Accumulator Arithmetic Logic Units (ALUs) which can encode (with implicit embedded extension) up to five levels of transformation. The proposed architecture, which consists of three adders, two subtractor-adders and five shifters, has a significantly lower hardware count compared to the architectures proposed by K. Andra et. al. (2002) and C-J. Lian et. al. (2001). In addition, the architecture has an efficient memory organisation, which uses lesser amount of embedded memory for processing and buffering. In this paper, we present the architecture and demonstrate that it closely adheres to the JPEG2000's specification while reducing the hardware requirements and hence area and power consumption.